mux 4x1 verilog programme by using 2x1 test bench

If parallel is used, XST will consider that the branches cannot occur in parallel and will not use a priority encoder.If full is used, XST will consider that Case statements are complete and will avoid latch creation.If the default is used, XST will implement the exact behavior of the Case statements.Accepted values for this parameter are default, full, parallel and full-parallel: This characterization of the Case statements can be guided or modified by using the Case Implementation Style parameter (Please refer to the 'Design Constraints' chapter for more details). XST automatically determines the characteristics of the Case statements and generates logic using Multiplexers, Priority Encoders and Latches that best implement the exact behavior of the Case statement. The following tables gives three examples of Case statements with different characteristics. PARALLEL if it does not contain branches that can be executed simultaneously.FULL if all possible branches are specified.If you use Verilog, then you have to be aware that Verilog Case statements can be full or not full, and they can also be parallel or not parallel. In the case that you do want to infer the MUX, you can force XST by using the design constraint called mux_extract.

For example, if the MUX has several inputs that are the same, then XST can decide not to infer it. Writing MUXs you can also use 'don't cares' to describe selector values.ĭuring the macro inference step, XST makes a decision to infer or not infer the MUXs. For example, if you describe a MUX using a Case statement, and you do not specify all values of the selector, you may get latches instead of a multiplexer. When writing MUXs, you must pay particular attention in order to avoid common traps. XST supports different description styles for multiplexers, such as If-Then-Else or Case.

Mux 4x1 verilog programme by using 2x1 test bench